Scalable Hardware & Systems Engineering (SHARE)
The Scalable Hardware & Systems Engineering (SHARE) consortium is pursuing two main research objectives: the development of electronic components and systems for future quantum computers, and semiconductor technology and integration for functional and scalable quantum-computing hardware.
In order to achieve the first objective, the quantum-computer microarchitecture will be addressed and interfaces to the quantum-computer architecture will be implemented. Hereby, the control and readout hardware must be customized regarding miniaturization to enable larger qubit systems. New concepts for the simultaneous generation of a high number of phase-locked arbitrary waveform signals and parallel readouts must be developed by elaborating partitioning concepts for highly integrated components, yet considering the overall performance concerning noise, phase and for decreased readout error rates and increased gate fidelities.
Targeting the second objective, development activities focus on: the exploration of new materials for superconducting qubit systems, the scalability and reproducibility of superconductive circuits and the establishment of a manufacturing technology on 200 mm industrial grade equipment. Technologies for hetero integration including flip-chip, through-silicon vias and flexible interconnects will be developed, as they are essential for the realization of large qubit systems. In the same time efficient procedures for cryo-testing and characterization will be established and interlaced with the development of manufacturing and integration processes.
New concepts for the simultaneous generation of a large number of phase-locked arbitrary signals and parallel readouts will be developed.
